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FEATURES 240 MSPS Throughput Rate 10-Bit D/A Converters SFDR -70 dB typ: fCLK = 50 MHz; fOUT = 1 MHz -53 dB typ: fCLK = 140 MHz; fOUT = 40 MHz RS-343A/RS-170 Compatible Output Complementary Outputs DAC Output Current Range: 2 mA to 26 mA TTL Compatible Inputs Internal Voltage Reference (1.23 V) on TSSOP Package Single Supply +5 V/+3.3 V Operation 28-Lead SOIC Package and 24-Lead TSSOP Package Low Power Dissipation (30 mW min @ 3 V) Low Power Standby Mode (10 mW min @ 3 V) Power-Down Mode (60 mW min @ 3 V) Power-Down Mode Available on TSSOP Package Industrial Temperature Range (-40 C to +85 C) APPLICATIONS Digital Video Systems (1600 1200 @ 100 Hz) High Resolution Color Graphics Digital Radio Modulation Image Processing Instrumentation Video Signal Reconstruction Direct Digital Synthesis (DDS) Wireless LAN GENERAL DESCRIPTION
CMOS, 240 MHz 10-Bit High Speed Video DAC ADV7127
FUNCTIONAL BLOCK DIAGRAM
VAA 10 D9-D0 DATA REGISTER 10 DAC IOUT
IOUT
PDOWN* PSAVE CLOCK
POWER- DOWN MODE
VOLTAGE* REFERENCE CIRCUIT
VREF
ADV7127
GND RSET COMP
*ON TSSOP VERSION ONLY
The ADV7127 (ADV(R)) is a high speed, digital-to-analog convertor on a single monolithic chip. It consists of a 10-bit, video D/A converter with on-board voltage reference, complementary outputs, a standard TTL input interface and high impedance analog output current sources. The ADV7127 has a 10-bit wide input port. A single +5 V/ +3.3 V power supply and clock are all that are required to make the part functional. The ADV7127 is fabricated in a CMOS process. Its monolithic CMOS construction ensures greater functionality with lower power dissipation. The ADV7127 is available in a small outline 28-lead SOIC or 24-lead TSSOP package.
The ADV7127 TSSOP package also has a power-down mode. Both ADV7127 packages have a power standby mode. The ADV7127 TSSOP package has an on-board voltage reference circuit. The ADV7127 SOIC package requires an external reference.
PRODUCT HIGHLIGHTS
1. 240 MSPS Throughput. 2. Guaranteed monotonic to 10 bits. 3. Compatible with a wide variety of high resolution color graphics systems including RS-343A and RS-170A.
ADV is a registered trademark of Analog Devices, Inc.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1998
ADV7127-SPECIFICATIONS
5 V SOIC SPECIFICATIONS
Parameter STATIC PERFORMANCE Resolution (Each DAC) Integral Nonlinearity (BSL) Differential Nonlinearity DIGITAL AND CONTROL INPUTS Input High Voltage, VIH Input Low Voltage, VIL Input Current, IIN PSAVE Pull-Up Current Input Capacitance, CIN ANALOG OUTPUTS Output Current Output Compliance Range, VOC Output Impedance, ROUT Output Capacitance, COUT Offset Error Gain Error2 VOLTAGE REFERENCE (Ext.) Reference Range, VREF POWER DISSIPATION Digital Supply Current3 Digital Supply Current3 Digital Supply Current3 Analog Supply Current Analog Supply Current Standby Supply Current4 Power Supply Rejection Ratio
(VAA = +5 V 5%, VREF = 1.235 V, RSET = 560 otherwise noted, TJ MAX = 110 C)
Min 10 -1 -1 2 -1 20 10 2.0 0 100 10 -0.025 -5.0 1.12 1.235 3.4 10.5 18 33 5 2.1 0.1 +0.025 +5.0 1.35 9 15 25 37 5.0 0.5 18.5 +1.4 0.8 +1 Typ Max
, CL = 10 pF. All specifications TMIN to TMAX 1 unless
Test Conditions
Units Bits LSB LSB V V A A pF mA V k pF % FSR % FSR V mA mA mA mA mA mA %/%
0.4 0.25
+1 +1
Guaranteed Monotonic
VIN = 0.0 V or VAA
IOUT = 0 mA Tested with DAC Output = 0 V FSR = 17.62 mA
fCLK = 50 MHz fCLK = 140 MHz fCLK = 240 MHz RSET = 560 RSET = 4933 PSAVE = Low, Digital and Control Inputs at VAA
NOTES 1 Temperature range T MIN to TMAX : -40C to +85C at 50 MHz and 140 MHz, 0C to +70C at 240 MHz. 2 Gain error = ((Measured (FSC)/Ideal (FSC) -1) x 100), where Ideal = V REF /RSET x K x (3FFH) and K = 7.9896. 3 Digital supply is measured with continuous clock with data input corresponding to a ramp pattern and with an input level at 0 V and V DD. 4 These max/min specifications are guaranteed by characterization to be over 4.75 V to 5.25 V range. Specifications subject to change without notice.
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ADV7127 5 V TSSOP SPECIFICATIONS
Parameter STATIC PERFORMANCE Resolution (Each DAC) Integral Nonlinearity (BSL) Differential Nonlinearity DIGITAL AND CONTROL INPUTS Input High Voltage, VIH Input Low Voltage, VIL PDOWN Input High Voltage2 PDOWN Input Low Voltage2 Input Current, IIN PSAVE Pull-Up Current PDOWN Pull-Up Current Input Capacitance, CIN ANALOG OUTPUTS Output Current Output Compliance Range, VOC Output Impedance, ROUT Output Capacitance, COUT Offset Error Gain Error3 VOLTAGE REFERENCE (Ext. and Int.)4 Reference Range, VREF POWER DISSIPATION Digital Supply Current5 Digital Supply Current5 Digital Supply Current5 Analog Supply Current Analog Supply Current Standby Supply Current6 PDOWN Supply Current2 Power Supply Rejection Ratio
(VAA = +5 V 5%, VREF = 1.235 V, RSET = 560 otherwise noted, TJ MAX = 110 C)
Min 10 -1 -1 2 0.8 3 1 -1 20 20 10 2.0 0 100 10 -0.025 -5.0 1.12 1.235 1.5 4 6.5 23 5 3.8 1 0.1 +0.025 +5.0 1.35 3 6 10 27 6 18.5 +1.4 +1 Typ Max
, CL = 10 pF. All specifications TMIN to TMAX1 unless
Test Conditions
Units Bits LSB LSB V V V V A A A pF mA V k pF % FSR % FSR V mA mA mA mA mA mA mA %/%
0.4 0.25
+1 +1
Guaranteed Monotonic
VIN = 0.0 V or VAA
IOUT = 0 mA Tested with DAC Output = 0 V FSR = 17.62 mA
fCLK = 50 MHz fCLK = 140 MHz fCLK = 240 MHz RSET = 560 RSET = 4933 PSAVE = Low, Digital and Control Inputs at VAA
0.5
NOTES 1 Temperature range T MIN to TMAX : -40C to +85C at 50 MHz and 140 MHz, 0C to +70C at 240 MHz. 2 This power-down feature is only available on the ADV7127 in the TSSOP package. 3 Gain error = ((Measured (FSC)/Ideal (FSC) -1) x 100), where Ideal = VREF /RSET x K x (3FFH ) and K = 7.9896. 4 Internal voltage reference is available only on the ADV7127 TSSOP package. 5 Digital supply is measured with continuous clock with data input corresponding to a ramp pattern and with an input level at 0 V and V DD. 6 These max/min specifications are guaranteed by characterization to be over 4.75 V to 5.25 V range. Specifications subject to change without notice.
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ADV7127-SPECIFICATIONS
3.3 V SOIC SPECIFICATIONS
Parameter STATIC PERFORMANCE Resolution (Each DAC) Integral Nonlinearity (BSL) Differential Nonlinearity DIGITAL AND CONTROL INPUTS Input High Voltage, VIH Input Low Voltage, VIL Input Current, IIN PSAVE Pull-Up Current Input Capacitance, CIN ANALOG OUTPUTS Output Current Output Compliance Range, VOC Output Impedance, ROUT Output Capacitance, COUT Offset Error Gain Error3 VOLTAGE REFERENCE (Ext.) Reference Range, VREF POWER DISSIPATION Digital Supply Current4 Digital Supply Current4 Digital Supply Current4 Analog Supply Current Analog Supply Current Standby Supply Current Power Supply Rejection Ratio
2 1 (VAA = +3.0 V-3.6 V, VREF = 1.235 V, RSET = 560 , CL = 10 pF. All specifications T MIN to T MAX
unless otherwise noted, TJ MAX = 110 C)
Min Typ Max 10 +1 +1
Units Bits LSB LSB V V A A pF mA V k pF % FSR % FSR V mA mA mA mA mA mA %/%
Test Conditions RSET = 680 RSET = 680 RSET = 680
-1 -1 2.0
0.5 0.25
0.8 -1 20 10 2.0 0 70 10 0 0 1.12 1.235 2.2 6.5 11 32 5 2.4 0.1 18.5 +1.4 +1
VIN = 0.0 V or VDD
0
Tested with DAC Output = 0 V FSR = 17.62 mA
1.35 5.0 12.0 15 35 5.0 0.5
fCLK = 50 MHz fCLK = 140 MHz fCLK = 240 MHz RSET = 560 RSET = 4933 PSAVE = Low, Digital and Control Inputs at VDD
NOTES 1 These max/min specifications are guaranteed by characterization to be over 3.0 V to 3.6 V range. 2 Temperature range T MIN to TMAX : -40C to +85C at 50 MHz and 140 MHz, 0C to +70C at 240 MHz. 3 Gain error = ((Measured (FSC)/Ideal (FSC) -1) x 100) , where Ideal = V REF /RSET x K x (3FFH) and K = 7.9896. 4 Digital supply is measured with continuous clock with data input corresponding to a ramp pattern and with an input level at 0 V and V DD. Specifications subject to change without notice.
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ADV7127 3.3 V TSSOP SPECIFICATIONS
Parameter STATIC PERFORMANCE Resolution (Each DAC) Integral Nonlinearity (BSL) Differential Nonlinearity DIGITAL AND CONTROL INPUTS Input High Voltage, VIH Input Low Voltage, VIL PDOWN Input High Voltage3 PDOWN Input Low Voltage3 Input Current, IIN PSAVE Pull-Up Current Input Capacitance, CIN ANALOG OUTPUTS Output Current Output Compliance Range, VOC Output Impedance, ROUT Output Capacitance, COUT Offset Error Gain Error4 VOLTAGE REFERENCE (Ext.) Reference Range, VREF VOLTAGE REFERENCE (Int.)5 Reference Range, VREF POWER DISSIPATION Digital Supply Current6 Digital Supply Current6 Digital Supply Current6 Analog Supply Current Analog Supply Current Standby Supply Current PDOWN Supply Current Power Supply Rejection Ratio
2 1 (VAA = +3.0 V-3.6 V, VREF = 1.235 V, RSET = 560 , CL = 10 pF. All specifications T MIN to T MAX
unless otherwise noted, TJ MAX = 110 C)
Typ Max 10 +1 +1
Min
Units Bits LSB LSB V V V V A A pF mA V k pF % FSR % FSR V V
Test Conditions RSET = 680 RSET = 680 RSET = 680
-1 -1 2.0
0.5 0.25
0.8 2.1 0.6 -1 20 10 2.0 0 70 10 0 0 1.12 1.235 1.235 1 2.5 4 22 5 2.6 20 0.1 2 4.5 6 25 3 18.5 +1.4 +1
VIN = 0.0 V or VDD
0
Tested with DAC Output = 0 V FSR = 17.62 mA
1.35
mA mA mA mA mA mA A %/%
fCLK = 50 MHz fCLK = 140 MHz fCLK = 240 MHz RSET = 560 RSET = 4933 PSAVE = Low, Digital and Control Inputs at VDD
0.5
NOTES 1 These max/min specifications are guaranteed by characterization to be over 3.0 V to 3.6 V range. 2 Temperature range T MIN to TMAX : -40C to +85C at 50 MHz and 140 MHz, 0C to +70C at 240 MHz. 3 This power-down feature is only available on the ADV7127 in the TSSOP package. 4 Gain error = ((Measured (FSC)/Ideal (FSC) -1) x 100), where Ideal = V REF /RSET x K x (3FFH) and K = 7.9896. 5 Internal voltage reference is available only on the ADV7127 TSSOP package. 6 Digital supply is measured with continuous clock with data input corresponding to a ramp pattern and with an input level at 0 V and V DD. Specifications subject to change without notice.
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ADV7127-SPECIFICATIONS
5 V/3.3 V DYNAMIC SPECIFICATIONS
Parameter DAC PERFORMANCE Glitch Impulse2, 3 Data Feedthrough2, 3 Clock Feedthrough2, 3
(VAA = (3 V-5.25 V)1, VREF = 1.235 V, RSET = 560 , CL = 10 pF. All specifications are for TA = +25 C unless otherwise noted, T J MAX = 110 C)
Min Typ 10 22 33 Max Units pVs dB dB
NOTES 1 These max/min specifications are guaranteed by characterization. 2 TTL input values are for 0 V and 3 V with input rise/fall times 3 ns, measured at the 10% and 90% points. Timing reference points at 50% for inputs and outputs. 3 Clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. Glitch impulse includes clock and data feedthrough. Specifications subject to change without notice.
5 V TIMING SPECIFICATIONS
Parameter ANALOG OUTPUTS Analog Output Delay, t6 Analog Output Rise/Fall Time, t74 Analog Output Transition Time, t85 Analog Output Skew, t96 CLOCK CONTROL fCLK7 fCLK7 fCLK7 Data and Control Setup, t1 Data and Control Hold, t2 Clock Pulsewidth High, t4 Clock Pulsewidth Low t5 Clock Pulsewidth High t4 Clock Pulsewidth Low t5 Clock Pulsewidth High t4 Clock Pulsewidth Low t5 Pipeline Delay, tPD6 PSAVE Up Time, t10 6 PDOWN Up Time, t118
1 (VAA = +5 V
Min
5%2, VREF = 1.235 V, RSET = 560 unless otherwise noted, TJ MAX = 110 C)
Typ 5.5 1.0 15 1 0.5 0.5 0.5 1.5 2.5 1.875 1.875 2.85 2.85 8.0 8.0 1.0 Max
, CL = 10 pF. All specifications T MIN to TMAX 3
Units ns ns ns ns MHz MHz MHz ns ns ns ns ns ns ns ns Clock Cycles ns ns 50 MHz Grade 140 MHz Grade 240 MHz Grade Condition
2 50 140 240
1.1 1.25
fMAX = 240 MHz fMAX = 240 MHz fMAX = 140 MHz fMAX = 140 MHz fMAX = 50 MHz fMAX = 50 MHz
1.0 2 320
1.0 10
NOTES 1 Timing specifications are measured with input levels of 3.0 V (V IH ) and 0 V (V IL) 0 for both 5 V and 3.3 V supplies. 2 These maximum and minimum specifications are guaranteed over this range. 3 Temperature range: T MIN to TMAX : -40C to +85C at 50 MHz and 140 MHz, 0C to +70C at 240 MHz. 4 Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition. 5 Measured from 50% point of full-scale transition to 2% of final value. 6 Guaranteed by characterization. 7 f CLK max specification production tested at 125 MHz and 5 V. Limits specified here are guaranteed by characterization. 8 This power-down feature is only available on the ADV7127 in the TSSOP package. Specifications subject to change without notice.
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ADV7127 3.3 V TIMING SPECIFICATIONS
Parameter ANALOG OUTPUTS Analog Output Delay, t6 Analog Output Rise/Fall Time, t74 Analog Output Transition Time, t85 Analog Output Skew, t96 CLOCK CONTROL fCLK7 fCLK7 fCLK7 Data and Control Setup, t26 Data and Control Hold, t26 Clock Pulsewidth High, t4 Clock Pulsewidth Low t56 Clock Pulsewidth High t46 Clock Pulsewidth Low t56 Clock Pulsewidth High t46 Clock Pulsewidth Low t56 Pipeline Delay, tPD6 PSAVE Up Time, t10 6 PDOWN Up Time, t118
3 2 1 (VAA = +3.0 V-3.6 V , VREF = 1.235 V, RSET = 560 . All specifications TMIN to TMAX unless
otherwise noted, TJ MAX = 110 C)
Min Typ 7.5 1.0 15 1
Max
Units ns ns ns ns MHz MHz MHz ns ns ns ns ns ns ns ns Clock Cycles ns ns
Condition
2 50 140 240
50 MHz Grade 140 MHz Grade 240 MHz Grade
1.5 2.5 1.1 1.4 2.85 2.85 8.0 8.0 1.0
fMAX = 240 MHz fMAX = 240 MHz fMAX = 140 MHz fMAX = 140 MHz fMAX = 50 MHz fMAX = 50 MHz
1.0 4 320
1.0 10
NOTES 1 Timing specifications are measured with input levels of 3.0 V (V IH ) and 0 V (V IL) 0 for both 5 V and 3.3 V supplies. 2 These maximum and minimum specifications are guaranteed over this range. 3 Temperature range: T MIN to T MAX : -40C to +85C at 50 MHz and 140 MHz, 0C to +70C at 240 MHz. 4 Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition. 5 Measured from 50% point of full-scale transition to 2% of final value. 6 Guaranteed by characterization. 7 f CLK max specification production tested at 125 MHz and 5 V limits specified here are guaranteed by characterization. 8 This power-down feature is only available on the ADV7127 in the TSSOP package. Specifications subject to change without notice.
t3 t4
CLOCK
t5
t2
DIGITAL INPUTS (D9-D0) DATA
t1
ANALOG OUTPUTS (IOUT, IOUT )
t8 t6 t7
NOTES: 1. OUTPUT DELAY (t6) MEASURED FROM THE 50% POINT OF THE RISING EDGE OF CLOCK TO THE 50% POINT OF FULL SCALE TRANSITION. 2. OUTPUT RISE/FALL TIME (t7) MEASURED BETWEEN THE 10% AND 90% POINTS OF FULL SCALE TRANSITION. 3. TRANSITION TIME (t8) MEASURED FROM THE 50% POINT OF FULL SCALE TRANSITION TO WITHIN 2% OF THE FINAL OUTPUT VALUE.
Figure 1. Timing Diagram
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ADV7127
ABSOLUTE MAXIMUM RATINGS 1 PIN CONFIGURATIONS 24-Lead TSSOP
VAA 1 D1 1 D2 2 D3 3 D4 4 D5 5 D6 6
24 23 22 21
VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V Voltage on any Digital Pin . . . . . GND - 0.5 V to VAA + 0.5 V Ambient Operating Temperature (TA) . . . . . -40C to +85C Storage Temperature (TS) . . . . . . . . . . . . . . -65C to +150C Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . +150C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300C Vapor Phase Soldering (1 Minute) . . . . . . . . . . . . . . . . 220C IOUT to GND2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to VAA
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Analog Output Short Circuit to any Power Supply or Common can be of an indefinite duration.
28-Lead SOIC
VAA VAA PSAVE RSET VREF COMP
28 27 26 25 24
D0 PSAVE RSET VREF COMP
D0 2 D1 3 D2 4 D3 5 D4 6 D5 7
ADV7127
20
ADV7127
23
TOP VIEW 19 IOUT D7 7 (Not to Scale) 18 IOUT D8 8 D9 9 VAA 10 PDOWN 11 NC 12
17 16 15 14 13
TOP VIEW 22 VAA D6 8 (Not to Scale) 21 IOUT D7 9
20 19 18 17 16 15
VAA GND GND CLOCK NC
VAA GND GND CLOCK VAA VAA
D8 10 D9 11 VAA 12 VAA 13 VAA 14
NC = NO CONNECT
ORDERING GUIDE1
Speed Options Package R-28 RU-243
2
50 MHz ADV7127KR50 ADV7127KRU50
140 MHz ADV7127KR140 ADV7127KRU140
240 MHz ADV7127JR240 ADV7127JRU240
NOTES 1 50 MHz and 140 MHz devices are specified for -40C to +85C operation; 240 MHz devices are specified for 0C to +70C. 2 SOIC Package. 3 TSSOP Package.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADV7127 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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ADV7127
PIN FUNCTION DESCRIPTIONS
Pin Mnemonic CLOCK
Function Clock Input (TTL Compatible). The rising edge of CLOCK latches the R0-R9, G0-G9, B0-B9, SYNC and BLANK pixel and control inputs. It is typically the pixel clock rate of the video system. CLOCK should be driven by a dedicated TTL buffer. Data Inputs (TTL Compatible). Data is latched on the rising edge of CLOCK. D0 is the least significant data bit. Unused data inputs should be connected to either the regular PCB power or ground plane. Current Output. This high impedance current source is capable of directly driving a doubly terminated 75 coaxial cable. Full-Scale Adjust Control. A resistor (RSET) connected between this pin and GND controls the magnitude of the full-scale video signal. Note that the IRE relationships are maintained, regardless of the full-scale output current. The relationship between RSET and the full-scale output current on IOUT is given by: IOUT (mA) = 7968 x VREF(V)/R SET() Compensation Pin. This is a compensation pin for the internal reference amplifier. A 0.1 F ceramic capacitor must be connected between COMP and VAA. Voltage Reference Input. An external 1.23 V voltage reference must be connected to this pin. The use of an external resistor divider network is not recommended. A 0.1 F decoupling ceramic capacitor should be connected between VREF and VAA. Analog Power Supply (5 V 5%). All VAA pins on the ADV7127 must be connected. Ground. All GND pins must be connected. Differential Current Output. Capable of directly driving a doubly terminated 75 load. If not required, this output should be tied to ground. Power Save Control Pin. The part is put into standby mode when PSAVE is low. The internal voltage reference circuit is still active on the TSSOP in this case. Power-Down Control Pin (24-Lead TSSOP Only). The ADV7127 completely powers down, including the voltage reference circuit, when PDOWN is low.
Reference Black Level
D0-D9 IOUT RSET
COMP VREF
VAA GND IOUT PSAVE PDOWN
TERMINOLOGY Color Video (RGB)
The maximum negative polarity amplitude of the video signal.
Reference White Level
This usually refers to the technique of combining the three primary colors of red, green and blue to produce color pictures within the usual spectrum. In RGB monitors, three DACs are required, one for each color.
Gray Scale
The maximum positive polarity amplitude of the video signal.
Video Signal
The discrete levels of video signal between reference black and reference white levels. A 10-bit DAC contains 1024 different levels, while an 8-bit DAC contains 256.
Raster Scan
That portion of the composite video signal which varies in gray scale levels between reference white and reference black. Also referred to as the picture signal, this is the portion that may be visually observed.
The most basic method of sweeping a CRT one line at a time to generate and display images.
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ADV7127 5 V-Typical Performance Characteristics
(VAA = +5 V, VREF = 1.235 V, I OUT = 17.62 A, 50
70 60 50 SFDR - dBc SFDR (SE) SFDR - dBc 40 30 20 10 0 SFDR (DE)
Doubly Terminated Load, Differential Output Loading, TA = +25 C)
80 70 60 50 40 30 20 10 SFDR (SE) SFDR - dBc 1.0 2.51 5.04 20.2 FREQUENCY - MHz 40.4 100 72.2 72.0 SFDR (DE) 71.8 71.6 71.4 71.2 71.0 70.8 70.6 70.4 -10 +25 +85 TEMPERATURE - C
0.1
1.0
2.51 5.04 20.2 FREQUENCY - MHz
40.4
100
0 0.1
Figure 2. SFDR vs. f OUT @ fCLOCK = 140 MHz (Single-Ended and Differential)
Figure 3. SFDR vs. fOUT @ fCLOCK = 50 MHz (Single-Ended and Differential)
Figure 4. SFDR vs. Temperature @ fCLOCK = 50 MHz (fOUT = 1 MHz)
76 74 72 70 4th HARMONIC 2nd HARMONIC
1.0 0.9 0.8
1.00 0.75 0.50 ERROR - LSB
LINEARITY - LSBs
3rd HARMONIC
0.7 0.6 0.5 0.4 0.3 0.2 0.1 LINEARITY vs. IOUT ERROR
THD - dBc
68 66 64 62 60 58 0 50 100 fCLOCK - MHz 140 160
0.00
1023 -0.16
-0.50
0.0
-1.00
0 2 IOUT/mA 17.62 20
CODE - INL
Figure 5. THD vs. f CLOCK @ fOUT = 2 MHz (2nd, 3rd and 4th Harmonics)
Figure 6. Linearity vs. I OUT
Figure 7. Typical Linearity
-5.0
2
-5.0 VAA = 5V CLK = 140MHz fOUT = 2.5MHz SING O/P SFDR - dBm VAA = 5V
2
-5.0 CLK = 140MHz fOUT = 20MHz SING O/P SFDR - dBc
2
VAA = 5V
CLK = 140MHz DUAL TONE DIFF O/P
SFDR - dBm
-45.0
-45.0
1
-45.0
1
1
-85.0
-85.0 0kHz START 35.0MHz 70.0MHz STOP 0kHz START 35.0MHz 70.0MHz STOP
-85.0 0kHz START 35.0MHz 70.0MHz STOP
Figure 8. SFDR (Single-Tone) @ fCLOCK = 140 MHz (fOUT1 = 2 MHz)
Figure 9. Single-Tone SFDR @ fCLOCK = 140 MHz (fOUT1 = 20 MHz)
Figure 10. Dual-Tone SFDR @ fCLOCK = 140 MHz (fOUT1 = 13.5 MHz, fOUT2 = 14.5 MHz)
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ADV7127 3 V-Typical Performance Characteristics
(VAA = +3 V, VREF = 1.235 V, I OUT =17.62 A, 50
70 60 50 SFDR - dBc SFDR (SE) SFDR - dBc 40 30 20 10 0 0.1
Doubly Terminated Load, Differential Output Loading, TA = +25 C)
80 SFDR (DE) 70 71.8 SFDR (SE) SFDR (fOUT = 1MHz) 71.6 SFDR - dBc 71.4 71.2 71.0 70.8 70.6 70.4 0 20 85 145 TEMPERATURE - C 165 72.0
SFDR (DE) 60 50 40 30 20 10 2.51 5.04 20.2 40.4 FREQUENCY - MHz 100 0 0.1 1.0
2.51 5.04 20.2 FREQUENCY - MHz
40.4
100
Figure 11. SFDR vs. f OUT @ fCLOCK = 140 MHz (Single-Ended and Differential)
Figure 12. SFDR vs. f OUT @ fCLOCK = 50 MHz (Single-Ended and Differential)
Figure 13. SFDR vs. Temperature @ fCLOCK = 50 MHz, (f OUT = 1 MHz)
76 2nd HARMONIC 74 72 70 THD - dBc 68 66 64 62 60 58 56 0 50 100 140 FREQUENCY - MHz 160 3rd HARMONIC 4th HARMONIC LINEARITY - LSBs
1.0 0.9 0.8
1.00 0.75 0.50
0.6 0.5 0.4 0.3 0.2 0.1 0.0
ERROR - LSB
0.7
0.00
1023
-0.50
-0.42
-1.00
0 2 17.62 IOUT - mA 20
CODE- INL
Figure 14. THD vs. fCLOCK @ fOUT = 2 MHz (2nd, 3rd and 4th Harmonics)
Figure 15. Linearity vs. IOUT
Figure 16. Typical Linearity
-5.0
2
-5.0 VAA = 3.3V CLK = 140MHz fOUT = 2.5MHz SING O/P VAA = 3.3V
2
-5.0 CLK = 140MHz fOUT = 20MHz SING O/P
2
VAA = 3.3V
CLK = 140MHz DUAL TONE SING O/P
SFDR - dBm
SFDR - dBm
-45.0
-45.0
1 1 1
-85.0
0kHz START
35.0MHz
70.0MHz STOP
-85.0
0kHz START
35.0MHz
70.0MHz STOP
SFDR - dBm
-45.0
-85.0
0kHz START
35.0MHz
70.0MHz STOP
Figure 17. Single-Tone SFDR @ fCLOCK = 140 MHz (fOUT1 = 2 MHz)
Figure 18. Single-Tone SFDR @ fCLOCK = 140 MHz (f OUT1 = 20 MHz)
Figure 19. Dual-Tone SFDR @ fCLOCK = 140 MHz (fOUT1 = 13.5 MHz, fOUT2 = 14.5 MHz)
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ADV7127
CIRCUIT DESCRIPTION AND OPERATION
The ADV7127 contains one 10-bit D/A converter, with one input channel containing a 10-bit register. A reference amplifier is also integrated on board the part.
Digital Inputs
All video data and control inputs are latched into the ADV7127 on the rising edge of CLOCK, as previously described in the Digital Inputs section. It is recommended that the CLOCK input to the ADV7127 be driven by a TTL buffer (e.g., 74F244).
IOUT mA 17.61 V 0.66 WHITE LEVEL
Ten bits of data (color information) D0-D9 are latched into the device on the rising edge of each clock cycle. This data is presented to the 10-bit DAC and is then converted to an analog output waveform. See Figure 20.
CLOCK
100 IRE
DIGITAL INPUTS D0-D9
DATA
0
0
BLACK LEVEL
Figure 21. IOUT Video Output Waveform
ANALOG OUTPUTS IOUT , IOUT
Figure 20. Video Data Input/Output
Table I. Video Output Truth Table (RSET = 560 RLOAD = 37.5 )
,
All these digital inputs are specified to accept TTL logic levels.
Clock Input
Description Data WHITE LEVEL VIDEO BLACK LEVEL
Power Management
IOUT 17.62 Video 0
IOUT
DAC Input
The CLOCK input of the ADV7127 is typically the pixel clock rate of the system. It is also known as the dot rate. The dot rate, and hence the required CLOCK frequency, will be determined by the on-screen resolution, according to the following equation: Dot Rate = (Horiz Res) x (Vert Res) x (Refresh Rate)/ (Retrace Factor) Horiz Res Vert Res Refresh Rate = Number of Pixels/Line. = Number of Lines/Frame. = Horizontal Scan Rate. This is the rate at which the screen must be refreshed, typically 60 Hz for a noninterlaced system or 30 Hz for an interlaced system.
0 3FF 17.62 - Video Data 17.62 000H
The PSAVE input of the ADV7127 puts the part into standby mode. It is used to reduce power consumption. When PSAVE is low, the power may be reduced to approximately 10 mW at 3 V. The ADV7127 in TSSOP package also has a power-down feature where the entire part, including the voltage reference circuit, is powered down. In this case, power on the ADV7127 can be reduced to 60 W at 3 V.
Table II. Power Management
Retrace Factor = Total Blank Time Factor. This takes into account that the display is blanked for a certain fraction of the total duration of each frame (e.g., 0.8). Therefore, if we have a graphics system with a 1024 x 1024 resolution, a noninterlaced 60 Hz refresh rate and a retrace factor of 0.8, then: Dot Rate = 1024 x 1024 x 60/0.8 = 78.6 MHz
Mode
ADV7127 TSSOP
ADV7127 SOIC
Power-Save 10 mW Typically at 3 V 10 mW Typically at 3 V Power-Down Power 60 W at 3 V Not Available
Reference Input
The ADV7127 has an on-board voltage reference. The VREF pin is normally terminated to VAA through a 0.1 F capacitor. Alternatively, the part could, if required, be overdriven by an external 1.23 V reference (AD1580). A resistance RSET connected between the RSET pin and GND determines the amplitude of the output video level according to the following equation: IOUT (mA) = 7,968 x VREF(V)/RSET() (1) Using a variable value of RSET, as shown in Figure 22, allows for accurate adjustment of the analog output video levels. Use of a fixed 560 R SET resistor yields the analog output levels as quoted in the specification page. These values typically correspond to the RS-343A video waveform values as shown in Figure 21.
The required CLOCK frequency is thus 78.6 MHz.
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ADV7127
D/A Converter Video Output Buffer
The ADV7127 contains a 10-bit D/A converter. The DAC is designed using an advanced, high speed, segmented architecture. The bit currents corresponding to each digital input are routed to either the analog output (bit = "1") or GND (bit = "0") by a sophisticated decoding scheme. The use of identical current sources in a monolithic design guarantees monotonicity and low glitch. The on-board operational amplifier stabilizes the full-scale output current against temperature and power supply variations.
Analog Output
The analog output of the ADV7127 is a high impedance current source. The current output is capable of directly driving a 37.5 load, such as a doubly terminated 75 coaxial cable. Figure 22 shows the required configuration for the output connected into a doubly terminated 75 load. This arrangement will develop RS-343A video output voltage levels across a 75 monitor.
IOUT DAC (CABLE) ZS = 75 (SOURCE TERMINATION) ZL = 75 (MONITOR) ZO = 75
The ADV7127 is specified to drive transmission line loads, which is what most monitors are rated as. The analog output configurations to drive such loads are described in the Analog Interface section and illustrated in Figure 23. However, in some applications it may be required to drive long "transmission line" cable lengths. Cable lengths greater than 10 meters can attenuate and distort high frequency analog output pulses. The inclusion of output buffers will compensate for some cable distortion. Buffers with large full power bandwidths and gains between two and four will be required. These buffers will also need to be able to supply sufficient current over the complete output voltage swing. Analog Devices produces a range of suitable op amps for such applications. These include the AD84x series of monolithic op amps. In very high frequency applications (80 MHz), the AD9617 is recommended. More information on line driver buffering circuits is given in the relevant op amp data sheets. Use of buffer amplifiers also allows implementation of other video standards besides RS-343A and RS-170. Altering the gain components of the buffer circuit will result in any desired video level.
Z2 +VS Z1 0.1 F ZO = 75 (CABLE) ZL = 75 (MONITOR)
IOUT
75 AD848 0.1 F -VS
Figure 22. Analog Output Termination for RS-343A
DAC ZS = 75 (SOURCE TERMINATION)
A suggested method of driving RS-170 video levels into a 75 monitor is shown in Figure 23. The output current level of the DAC remains unchanged, but the source termination resistance, ZS, on the DAC is increased from 75 to 150 .
IOUT DAC (CABLE) ZS = 150 (SOURCE TERMINATION) ZL = 75 (MONITOR) ZO = 75
GAIN (G) = 1 +
Z1 Z2
Figure 24. AD848 As an Output Buffer
PC Board Layout Considerations
The ADV7127 is optimally designed for lowest noise performance, both radiated and conducted noise. To complement the excellent noise performance of the ADV7127 it is imperative that great care be given to the PC board layout. Figure 25 shows a recommended connection diagram for the ADV7127. The layout should be optimized for lowest noise on the ADV7127 power and ground lines. This can be achieved by shielding the digital inputs and providing good decoupling. The lead length between groups of VAA and GND pins should be minimized to inductive ringing.
Ground Planes
Figure 23. Analog Output Termination for RS-170
More detailed information regarding load terminations for various output configurations, including RS-343A and RS-170, is available in an Application Note entitled "Video Formats & Required Load Terminations" available from Analog Devices, publication no. E1228-15-1/89. Figure 21 shows the video waveforms associated with the current output driving the doubly terminated 75 load of Figure 22.
Gray Scale Operation
The ADV7127 can be used for stand-alone, gray scale (monochrome) or composite video applications (i.e., only one channel used for video information).
The ADV7127 and associated analog circuitry, should have a separate ground plane referred to as the analog ground plane. This ground plane should connect to the regular PCB ground plane at a single point through a ferrite bead, as illustrated in Figure 25. This bead should be located as close as possible (within 3 inches) to the ADV7127. The analog ground plane should encompass all ADV7127 ground pins, voltage reference circuitry, power supply bypass circuitry, the analog output traces and any output amplifiers. The regular PCB ground plane area should encompass all the digital signal traces, excluding the ground pins, leading up to the ADV7127.
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ADV7127
Power Planes Supply Decoupling
The PC board layout should have two distinct power planes, one for analog circuitry and one for digital circuitry. The analog power plane should encompass the ADV7127 (VAA) and all associated analog circuitry. This power plane should be connected to the regular PCB power plane (VCC) at a single point through a ferrite bead, as illustrated in Figure 25. This bead should be located within three inches of the ADV7127. The PCB power plane should provide power to all digital logic on the PC board, and the analog power plane should provide power to all ADV7127 power pins, voltage reference circuitry and any output amplifiers. The PCB power and ground planes should not overlay portions of the analog power plane. Keeping the PCB power and ground planes from overlaying the analog power plane will contribute to a reduction in plane-to-plane noise coupling.
Noise on the analog power plane can be further reduced by the use of multiple decoupling capacitors (see Figure 25). Optimum performance is achieved by the use of 0.1 F ceramic capacitors. Each of the two groups of VAA should be individually decoupled to ground. This should be done by placing the capacitors as close as possible to the device with the capacitor leads as short as possible, thus minimizing lead inductance. It is important to note that while the ADV7127 contains circuitry to reject power supply noise, this rejection decreases with frequency. If a high frequency switching power supply is used, the designer should pay close attention to reducing power supply noise. A dc power supply filter (Murata BNX002) will provide EMI suppression between the switching power supply and the main PCB. Alternatively, consideration could be given to using a three terminal voltage regulator.
COMP C6 0.1 F VAA
ANALOG POWER PLANE
ADV7127
VREF D0 D9
C3 0.1 F
C4 0.1 F
C5 0.1 F
L1 (FERRITE BEAD) +5V (VCC)
VIDEO DATA INPUTS
C2 10 F ANALOG GROUND PLANE GND
C1 33 F GROUND
PDOWN PSAVE CLOCK RSET IOUT
RSET 560
R1 75
L2 (FERRITE BEAD)
VIDEO OUTPUT
COMPONENT C1 C2 C3, C4, C5, C6 L1, L2 R1 RSET
DESCRIPTION
VENDOR PART NUMBER
33 F TANTALUM CAPACITOR 10 F TANTALUM 0.1 F CERAMIC CAPACITOR FERRITE BEAD FAIR-RITE 274300111 OR MURATA BL01/02/03 75 1% METAL FILM RESISTOR DALE CMF-55C 560 1% METAL FILM RESISTOR DALE CMF-55C
Figure 25. Typical Connection Diagram and Component List
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Digital Signal Interconnect
The digital signal lines to the ADV7127 should be isolated as much as possible from the analog outputs and other analog circuitry. Digital signal lines should not overlay the analog power plane. Due to the high clock rates used, long clock lines to the ADV7127 should be avoided so as to minimize noise pickup. Any active pull-up termination resistors for the digital inputs should be connected to the regular PCB power plane (VCC), and not the analog power plane.
Analog Signal Interconnect
The video output signals should overlay the ground plane, and not the analog power plane, thereby maximizing the high frequency power supply rejection. For optimum performance, the analog outputs should each have a source termination resistance to ground of 75 (doubly terminated 75 configuration). This termination resistance should be as close as possible to the ADV7127 so as to minimize reflections. Additional information on PCB design is available in an application note entitled "Design and Layout of a Video Graphics System for Reduced EMI." This application note is available from Analog Devices, publication number E1309-15-10/89.
The ADV7127 should be located as close as possible to the output connectors thus minimizing noise pickup and reflections due to impedance mismatch.
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ADV7127
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead SOIC (R-28)
0.7125 (18.10) 0.6969 (17.70)
28 15
1
14
PIN 1
0.1043 (2.65) 0.0926 (2.35)
0.4193 (10.65) 0.3937 (10.00)
0.2992 (7.60) 0.2914 (7.40)
0.0291 (0.74) x 45 0.0098 (0.25)
0.0118 (0.30) 0.0040 (0.10)
0.0500 (1.27) BSC
8 0.0500 (1.27) 0.0192 (0.49) 0 0.0157 (0.40) SEATING 0.0125 (0.32) 0.0138 (0.35) PLANE 0.0091 (0.23)
24-Lead TSSOP (RU-24)
0.311 (7.90) 0.303 (7.70)
24 13
0.177 (4.50) 0.169 (4.30)
1
12
0.006 (0.15) 0.002 (0.05)
PIN 1 0.0433 (1.10) MAX 0.0256 (0.65) 0.0118 (0.30) BSC 0.0075 (0.19) 0.028 (0.70) 0.020 (0.50)
SEATING PLANE
0.256 (6.50) 0.246 (6.25)
8 0 0.0079 (0.20) 0.0035 (0.090)
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PRINTED IN U.S.A.
C3259-8-4/98

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